This disclosure relates to integrated circuit devices, and more specifically, to a method and structure to create advanced Si and SiGe FinFET structures in semiconductor devices.
As the dimensions of modern integrated circuitry in semiconductor chips continues to shrink, conventional lithography is increasingly challenged to make smaller and smaller structures. With the reduced size of the integrated circuit, packaging the chips more closely together becomes important as well. By placing chips closer to each other, the performance of the overall computer system is improved.
FinFET (Fin Field Effect Transistor) has become a preferred CMOS technology at 22 nm. The semiconductor industry has found an alternative approach to planar FETs with FinFETs to reduce leakage current in semiconductor devices. In a FinFET, an active region including the drain, the channel region and the source protrudes up in a “fin” from the surface of the semiconductor substrate upon which the FinFET is located. Due to the many superior attributes, especially in the areas of device performance, off-state leakage and footprint, FinFETs are replacing planar FETs. CMOS FinFET devices have both FinFETs which use n-channels (nFETs) and FinFETs which use p-channels (pFETs). In some devices, different channel materials are being developed for each type of transistor, i.e. nFET versus pFET, in advanced integrated circuits. For example, there is a class of FinFETs which use silicon channels for nFETs and silicon germanium channels for pFETs. However, due to the different materials used in the respective channels, it is difficult to provide isolation for both the n-channel FinFETs and p-channel FinFETs at small geometries.
Therefore, there is a need for improving CMOS FinFET fabrication technologies.